This invention is in the field of semiconductor integrated circuits, and is more specifically directed to the low-cost fabrication of heterojunction bipolar silicon-on-insulator (SOI) integrated circuits.
As is well known in the art, the emitter injection efficiency, or simply emitter efficiency, of a bipolar transistor is a significant factor in the switching speed of the device. Emitter efficiency is generally defined as the ratio of electron current to hole current across the forward-biased emitter-base junction. In general, for “homojunction” transistors, which are transistors formed of a single material, the emitter injection efficiency is effectively proportional to the ratio of dopant concentration in the emitter region to the dopant concentration in the base region. However, this ratio is limited by such other factors as junction breakdown voltage, and the requirements for high Early voltages.
A method of improving this injection efficiency is to replace the conventional emitter-base homojunction with a heterojunction, in which the emitter material is different from that of the base. In conventional heterojunction devices, this difference has the effect of reducing the energy barrier to carriers that are injected from the emitter into the base region, thus improving emitter efficiency. In addition, conventional heterojunction devices are constructed so that a built-in electric field is present in the base region. This built-in field assists in carrier transport across the base region from the emitter to the collector, reducing the cutoff frequency fT of the device and improving the switching performance of the device. Examples of materials used in conventional heterojunction devices include gallium arsenide, gallium-aluminum arsenide, indium-phosphorous, other periodic group III-V material pairs, and these materials combined with silicon (e.g., silicon-gallium-arsenide).
Another conventional heterojunction bipolar transistor is formed in silicon, with an emitter is formed of silicon and a base is formed of a silicon-germanium alloy. Because the silicon-germanium structure has a narrower band gap than silicon, this heterojunction device has improved carrier injection efficiency from the emitter into the base, resulting in higher current gain. The high-frequency characteristics of the heterojunction device can be improved by grading the germanium profile in the silicon-germanium base, providing a built-in electric field that sweeps minority carriers through the base to the collector. It has been observed that silicon-germanium devices can provide comparable performance as GaAs in devices such as power amplifiers, at the added benefit of a substantial reduction in manufacturing cost.
However, conventional manufacturing processes for forming heterojunction devices of reasonable performance are very costly. For example, molecular beam epitaxy is generally used for many materials, such as gallium arsenide and the like. In the case of silicon-germanium heterojunction devices, the silicon-germanium films are formed by epitaxial growth from an underlying silicon layer. Such epitaxy is quite difficult and costly, especially considering the differences in lattice constant between silicon and germanium. Detrimental effects of this lattice mismatch between the silicon-germanium and the silicon substrate is also often present in these conventional methods, include high leakage current and low breakdown, especially as the germanium content in the silicon-germanium increases and the critical thickness decreases.
By way of further background, silicon-on-insulator (SOI) technology has also proven to be advantageous for high performance transistors. As is well-known in the art, SOI devices are formed in a relatively thin layer of single-crystal silicon overlying an insulating layer, such as silicon dioxide. The presence of the insulating layer largely eliminates the presence of junction capacitance, most importantly for transistor collectors, in the bipolar context. In conventional bulk devices, significant capacitance is present at the reverse-biased p-n junction between the transistor collector and the underlying substrate. In contrast, there is no p-n junction surrounding the collector in an SOI device; rather, the collector region interfaces with the underlying insulator film. Because the underlying insulator is relatively thick, little parasitic capacitance is presented to the device collector, and the switching speed of the SOI transistor is improved accordingly.
By way of further background, U.S. Pat. No. 5,583,059 describes a heterojunction transistor formed on in an SOI structure. According to this approach, the emitter and silicon-germanium base are arranged in vertical fashion, in connection with an extremely thin lateral collector. According to this reference, the silicon-germanium base is grown by epitaxy.